1. Field of the Invention
Example embodiments of the present invention may generally relate to a semiconductor chip stack structure and method thereof, and more particularly, to a multi-chip package and a method for manufacturing the multi-chip package.
2. Description of the Related Art
With the reduction in size of today's portable electronic devices, semiconductor packages are also moving toward a reduction in size. To meet the demands for smaller packaging, multi-chip packaging techniques have been introduced, for example. Multi-chip packages (MCPs) may include a plurality of semiconductor chips in a single package. MCPs may produce high integration, size reduction and/or lighter weight.
FIG. 1 is a perspective view of a conventional multi-chip package. FIG. 2 is a cross-sectional view taken along the line of I-I′ of FIG. 1.
Referring to FIGS. 1 and 2, the conventional multi-chip package may include a substrate 21 and semiconductor chips 23 and 25. The semiconductor chip 23 is hereinafter referred to as a lower semiconductor chip and the semiconductor chip 25 is hereinafter referred to as an upper semiconductor chip. The upper semiconductor chip 25 may be stacked on the lower semiconductor chip 23, for example, which may be called an overhang type chip stack structure. The lower and upper semiconductor chips 23 and 25 may have the same size and/or function. The lower semiconductor chip 23 may be attached to the substrate 21 using a lower adhesive 22. The upper semiconductor chip 25 may be attached to the lower semiconductor chip 23 using an upper adhesive 27. The lower and upper semiconductor chips 23 and 25 may be rectangular semiconductor chips (e.g., a side D1 of the upper semiconductor chip 25 may be longer than a side D2 of the lower semiconductor chip 23, as shown in FIG. 2). Therefore, the upper semiconductor chip 25 may have overhang portions H1 at one or more ends, as also shown in FIG. 2.
The substrate 21 may have first substrate pads 31 and second substrate pads 35. The lower semiconductor chip 23 may have lower chip pads 23a formed along opposite edges. The lower chip pads 23a may be connected to the first substrate pads 31 of the substrate 21 using first bonding wires 29. Similarly, the upper semiconductor chip 25 may have upper chip pads 25a formed along opposite edges. The upper chip pads 25a may be connected to the second substrate pads 35 of the substrate 21 using second bonding wires 33. The first and second bonding wires 29 and 33 may be formed using, for example, a capillary 41.
During a wire bonding process, a conventional multi-chip package may encounter problems, for example, contact failures and/or crack generation of the semiconductor chips. Specifically, the capillary 41 may apply a downward force on the upper chip pads 25a when forming the second bonding wires 33. The pressing force of the capillary 41 may warp and/or bend the upper semiconductor chip 25 in the direction of A1 and/or A2. As a result, this may lead to contact failures between the second bonding wires 33 and the upper chip pads 25a of the upper semiconductor chip 25. Further, warpage or bending of the upper semiconductor chip 25 may create cracks at the overhang portion H1, thereby increasing the defect ratio in a semiconductor manufacturing process. Such problems may be significant when the thickness of the semiconductor chip 25 is reduced, the thickness of the semiconductor chip 23 is increased, and/or the length L of the overhang portion H1 is increased.
Conventionally, in order to solve the above problems, a rest member or other support member may be interposed between an upper semiconductor chip and a substrate to prevent and/or reduce warpage of the upper semiconductor chip. However, the conventional art may require additional processes for forming the rest member or support member between the upper semiconductor chip and the substrate, which may reduce the productivity during a semiconductor manufacturing process and/or may increase manufacturing costs.